Pipelined MIPS Processor
Computer Architecture (CprE 381) final lab project
VHDL, ModelSim, understanding of processor microarchitecture design, MIPS ISA, MIPS programming, Git
Working in a team of three, we developed a five-stage pipelined processor design that implemented a subset of the MIPS ISA. We ran compiled MIPS on our simulated design that used the full subset, testing all potential hazards and forwarding cases. We completed each stage of the project early and missed no points on the project.
This project reinforced power of proper planning and documentation. We made very detailed diagrams (collaboratively using Google Drawing) that were more or less a one-to-one correspondence to our final VHDL. This aided the compression, coding, and debugging process immensely.